1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to an array substrate of an LCD and a method of manufacturing the same.
2. Description of the Related Art
An LCD is considered to be the next generation of display device because it has good portability and low power consumption, and also has a good performance in terms of resolution and digital adaptability. The LCD is a non-self-luminous display device in which liquid crystal is positioned between a color filter substrate and an array substrate having a thin film transistor (TFT). An image is displayed by using the anisotropy of the liquid crystal and the different refractivity of light transmitted through the LCD from a backlight unit.
An active matrix (AM) LCD is typically used as an LCD. In the AMLCD, a TFT is positioned in each of the pixels. The TFT serves as a switching device that adjusts the arrangement of the liquid crystals in the pixel to change the transmittance of the pixel. Such a TFT is generally formed of amorphous silicon (a-Si). The reason for the use of a-Si is that numerous a-Si TFTs can be easily formed over a large area by depositing a-Si at a temperature less than 350° C., patterning the a-Si, doping the a-Si, and then depositing a low-priced insulating layer at a temperature less than 350° C.
Amorphous silicon has a disordered atomic arrangement in which the Si—Si bonding is weak and also a dangling bond. Accordingly, when light or an electric field is applied thereto, amorphous silicon is changed into a quasi-stable state, which is unstable for use as a TFT. More specifically, the electrical characteristics of the amorphous silicon degrade as a result of light irradiation, and thus light irradiated a-Si is difficult to use for a driving circuit due to its low electric field mobility (0.1-1.0 cm2/V·s) and low reliability. Also, since the a-Si TFT array substrate and a printed circuit board (PCB) with the driving IC for the a-Si TFT array substrate are connected by having the driving IC on a tape carrier package (TCP), the installation cost and the cost of the driving IC occupies a large part of the manufacturing cost. Further, when the resolution of the LCD increases, it is difficult to perform the bonding process between the a-Si TFT array substrate and the TCP because a pad pitch for connecting the gate and data lines of the a-Si TFT array substrate to the TCP becomes smaller.
Polysilicon has higher electric field mobility than the amorphous silicon. Polysilicon can be used in driving circuits that are directly mounted on the TFT array substrate of a high resolution panel. Further, polysilicon can be used for the TFT switching device of the high-resolution panel when the driving circuit is directly mounted on the array substrate because the driving circuit is also made of polysilicon. Thus, the cost for connecting the driving IC can be reduced and the driving IC can be simply mounted. In addition, the polysilicon can be efficiently used in a display device transmitting a large amount of light because polysilicon has a smaller photocurrent than amorphous silicon.
The structure of a TFT of a related art LCD will now be described in detail with reference to FIGS. 1A and 1B. Respectively, FIG. 1A is a cross-sectional view of a TFT in a pixel unit of a related art LCD and FIG. 1B is a cross-sectional view of a CMOS TFT in a driving circuit unit of a related art LCD. Both the pixel unit and the driving circuit unit include a top gate type TFT having a gate electrode disposed above the semiconductor layer of the TFT.
Referring to FIG. 1A, a TFT unit I of a pixel region of a related art LCD includes: a transparent insulating substrate 101 as a substrate, a buffer layer 114 formed on the insulating substrate 101, a semiconductor layer 116 formed on the buffer layer 114, and a gate insulating layer 118 and a gate electrode 120 sequentially stacked on the semiconductor layer 116. An interlayer insulating layer 124, including first and second semiconductor contact holes 122a and 122b, is formed over the gate electrode 120 and the gate insulating layer 118. Source and drain electrodes 126 and 128 are formed on the interlayer insulating layer 124 to overlap the gate electrode 120 and to be spaced apart from each other by a predetermined distance. The source and drain electrodes 126 and 128 are connected to the semiconductor layer 116 through the first and second semiconductor contact holes 122a and 122b, respectively.
A passivation layer 132 including a drain contact hole 130 is formed over the source and drain electrodes 126 and 128, and the interlayer insulating layer 124. A pixel electrode 134 is formed on the passivation layer 132. The pixel electrode 134 is connected to the drain electrode 128 through the drain contact hole 130.
The semiconductor layer 116 includes: an n+ impurity regions 116c respectively contacting the source electrode 126 and drain electrode 128, an active region 116a between the n+ impurity regions 116c, and lightly doped drain (LDD) regions 116b respectively formed between the active region 116a and the n+ impurity regions 116c contacting the source and drain electrodes 126 and 128. The LDD regions 116b are provided for hot carrier distribution. Thus, the LDD regions 116b are doped at a low concentration to prevent the loss on-state current as well as to prevent leakage current.
Referring to FIG. 1B, a CMOS TFT of the driving circuit unit includes a TFT unit II having a channel doped with n-type ions, and a TFT unit III having a channel doped with p-type ions. The same reference numerals are used to denote the same elements.
A buffer layer 114 is formed on a transparent insulating substrate 101. An n-type semiconductor layer 140 and a p-type semiconductor layer 142 are formed on a buffer layer 114 such that they are spaced apart from each other by a predetermined distance. Gate insulating layers 144a and 144b and gate electrodes 146a and 146b are formed on the n-type semiconductor layer 140 and the p-type semiconductor layer 142, respectively. An interlayer insulating layer 124, including semiconductor layer contact holes 147a, 147b, 147c and 147d, is formed on the gate electrodes 146a and 146b, and over the gate insulating layers 144a and 144b. 
Source electrodes 150a and 150b and drain electrodes 152a and 152b are formed on the interlayer insulating layer 124 such that they are respectively connected to the n-type semiconductor layer 140 and the p-type semiconductor layer 142 through the semiconductor layer contact holes 147a, 147b, 147c and 147d. A passivation layer 132 is formed on the source electrodes 150a and 150b and also on the drain electrodes 152a and 152b as well as over the surface of the interlayer insulating layer 124.
The n-type semiconductor layer 140 includes: an n+ impurity regions 140c respectively contacting the source electrode 150a and drain electrode 152a, an active region 140a between the n+ impurity regions 140c, and lightly doped drain (LDD) regions 140b between the active region 140a and the n+ impurity regions 140c. Since the p-type semiconductor layer 142 of the p-type TFT unit III is formed to use carriers charged with a positive charge, it is less affected by a leakage current and degradation of carriers than the n-type TFT unit II. Thus, the p-type semiconductor layer 142 of the p-type TFT unit III does not include LDD regions. Accordingly, the p-type semiconductor layer 142 includes: a p-type impurity regions 142b respectively contacting the source electrode 150b and the drain electrode 152b, and an active region 142a between the p-type impurity regions 142b. 
A method of manufacturing the TFT of the pixel unit and the CMOS TFT of the driving circuit unit will now be described with reference to FIG. 2, which is a flow chart illustrating a method of manufacturing the related art LCD. Each of the processes in the method shown in FIG. 2 includes a photolithography process (hereinafter referred to as a “mask process”) using a photoresist (PR).
As shown in FIG. 2, an active layer and a first capacitor electrode are formed in process 200. First, a buffer layer is formed on a transparent insulating substrate. The buffer layer is formed mainly of an inorganic insulating layer, such as a silicon nitride (SiNx) layer or a silicon oxide (SiOx) layer. Thereafter, amorphous silicon is deposited on the buffer layer. The amorphous silicon is dehydrogenated and crystallized to form crystalline silicon, such as monocrystalline silicon or polycrystalline silicon. A first mask process is performed on the crystalline silicon to form the active layer and the first capacitor electrode.
In process 201, as shown in FIG. 2, a second mask process is performed to expose the first capacitor electrode so as to dope the first capacitor electrode. A photoresist pattern is formed to cover the active layer. Thereafter, the first capacitor electrode is doped with n+ impurities using the photoresist pattern as a mask. Thereafter, the photoresist pattern is stripped.
In process 202, as shown in FIG. 2, a gate insulating layer and a gate electrode are formed. A silicon nitride layer and aluminum (Al) is sequentially deposited on the substrate having the active layer. Then, the gate insulating layer and the gate electrode are formed through a third mask process.
In process 203, as shown in FIG. 2, an n-type semiconductor layer is formed. N-impurities are doped onto the substrate including the gate insulating layer and the gate electrode to form LDD regions in the semiconductor layer. Thereafter, n+ impurity regions are formed into the semiconductor layer with n+ impurities doped through a fourth mask process.
In process 204, as shown in FIG. 2, a p-type semiconductor layer is formed. P-type impurity regions doped with p+impurities are formed on the substrate having the n-type semiconductor layer through a fifth mask process.
In process 205, as shown in FIG. 2, an interlayer insulating layer is formed. An inorganic insulating layer (e.g., a silicon nitride layer or a silicon oxide layer) is deposited on the substrate having both the p-type semiconductor layer and n-type semiconductor layer. Then, contact holes for contacting the semiconductor layers are formed in the interlayer insulating layer through a sixth mask process.
In process 206, as shown in FIG. 2, source and drain electrodes are formed. Molybdenum (Mo) and aluminum neodymium (AINd) are sequentially deposited on the interlayer insulating layer. A batch etching is then performed through a seventh mask process to form the source and drain electrodes connected to the impurity regions through the contact holes.
In process 207, as shown in FIG. 2, a passivation layer is formed. A silicon nitride layer is formed over the source and drain electrodes on the substrate. Thereafter, the silicon nitride layer is thermally hydrogenated. At this time, the thermal hydrogenation process includes an annealing process and is performed once using N2 gas at 380° C. The thermal hydrogenation process serves to move hydrogen contained in the silicon nitride layer to the bottom surface. In the TFT unit I of the pixel unit, a drain contact hole for contacting with the drain electrode is formed in the passivation layer through an eighth mask process.
In process 208, as shown in FIG. 2, a pixel electrode is formed. This process further builds the TFT unit I of the pixel unit. An indium tin oxide (ITO) is deposited on the passivation layer. The pixel electrode connected to the drain electrode through the drain contact hole is formed through a ninth mask process, which etches the ITO.
As described above, the related art method of manufacturing the LCD requires nine mask processes. Nine mask processes require a large amount of time and are costly. Accordingly, researches are actively conducted to reduce the number of the mask processes. When the number of the mask processes is reduced, manufacturing time and cost are reduced.